1. Technical Field
The present invention relates to a test apparatus. Particularly, the present invention relates to a test apparatus which tests the jitter tolerance of a receiving circuit, by applying a jitter to a transmission signal output from a transmitting circuit and inputting the signal to the receiving circuit.
2. Related Art
As a test on a device under test such as a semiconductor circuit, etc., such a test is known, which measures the jitter tolerance of the device under test. This test examines the jitter tolerance of the device under test, by varying the amplitude of the jitter to be applied to the signal to be input to the device under test, and measuring the range of jitter amplitudes within which the device under test can operate normally.
Further, there is known a technique which uses the above-described test in the loopback test on a SerDes circuit, for example, as disclosed in U.S. Pat. No. 7,017,087. In this test, a jitter means applies a jitter having a desired amplitude to a signal output from a transmitter Tx in the SerDes circuit, and inputs the signal to a receiver Rx in the SerDes circuit. The jitter tolerance of the receiver Rx can be measured from the range of the amounts of jitters applied, within which the receiver Rx has operated normally.
In this case, in order to precisely measure the jitter tolerance, it is preferable to precisely control the amount of the jitter to be included in the signal to be input to the receiver Rx. However, the signal to be input to the receiver Rx includes not only the jitter applied by the jitter applying means, but jitters that have occurred in the transmitter Tx, etc.
Therefore, according to the conventional test, errors can be included in the values measured as the jitter tolerance, due to the jitters that have occurred in the transmitter Tx, etc. Though it is conceivable to control the jitters which can occur in the transmitter Tx, etc., it is difficult to precisely control such jitters that can occur in the transmitter Tx, etc.